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Message-ID: <d9f567447c3a36fc919d22cb750aeca9@smtp.hushmail.com>
Date: Sat, 25 Apr 2015 20:06:25 +0200
From: magnum <john.magnum@...hmail.com>
To: john-dev@...ts.openwall.com
Subject: Re: [GSoC] JtR SIMD support enhancements
On 2015-04-25 14:34, Solar Designer wrote:
>> Benchmarking: NT [MD4 32/64]... DONE
>> Raw: 3509K c/s real, 3509K c/s virtual
>
> No MIC code for it yet?
You mean hand crafted assembler? If not I can't see what would be the
point considering we have NT2. This format is obsolete for AVX2 builds
too (NT2 benches nearly 100M). I think we might want to phase it out (at
least rename it to nt-sse2 or something) in favor of NT2 (which I'd
prefer to have as "NT" from now on). That is, unless someone actually
adds stuff to the assembler code soon.
>> Benchmarking: nt2, NT [MD4 512/512 MIC 16x]... DONE
>> Raw: 4907K c/s real, 4907K c/s virtual
>
> Very little improvement relative to the "NT" format. I expected more of
> a difference. Perhaps this will be seen with --fork=240. I guess the
> SIMD instructions have higher latency, so impact the case of running
> only one thread/core more. Need to run 4 threads/core here.
I suppose that also means bumping the interleaving factors will make a
whole lot of difference, more than we're used to. Considering this run
was without ANY interleaving I'm curious what results we'll see.
I don't really have a good understanding of the MIC. Is there only 60
real cores? Is there some kind of HT involved too or why is it 240
threads by default? Is it more like 60 real quad-cores but with some
bottlenecks between them?
BTW I think we (at least I) have always established the interleaving
factors by benching a non-OpenMP build. Not sure if that's sensible here.
magnum
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