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Message-ID: <CA+EaD-ZnDMsnL+ptYGF2sU8+Oi9dcVciZLCQW-UYez15uv4J3A@mail.gmail.com>
Date: Sat, 21 Sep 2013 18:40:34 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: ZedBoard / Parallella: bcrypt
On Sat, Sep 21, 2013 at 5:22 PM, Katja Malvoni <kmalvoni@...il.com> wrote:
> I don't know yet, I'm trying 125 MHz at the moment.
>
It also fails timing analysis but both bcrypt format work. Performance is
50.5 c/s which doesn't make sense (expected is 45 c/s + communication
overhead).
Parallella part doesn't meet timing constraints but I don't understand why.
I haven't changed FCLK3 so it should be OK. I also changed FCLK1 constraint
to be 125 MHz and it's still 200 MHz. I tried connecting bcrypt to FCLK0
and leaving FCLK1 on 150 MHz. In that case, timing constraints are met and
bcrypt works. If I connect it to FCLK1 or FCLK2 I have timing problems
although both bcrypt formats work. I can't change FCLK0 because FCLK0 at
100 MHz is necessary for Epiphany to work.
----------------------------------------------------------------------------------------------------------
Constraint
| Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_parallella_rx_outclock = PERIOD TIMEGR | SETUP |
6.943ns | 6.093ns| 0 | 0
P "parallella_rx_outclock" TS_rxi_lclk_p | HOLD
| -0.924ns | | 1541 | 414974
* 4 HIGH 50% INPUT_JITTER 0.1 ns |
| | | |
----------------------------------------------------------------------------------------------------------
* TS_clk_fpga_3 = PERIOD TIMEGRP "clk_fpga_ | SETUP | 21.717ns
| 3.283ns| 0 | 0
3" 40 MHz HIGH 50% | HOLD
| -0.327ns | | 505 | 115049
----------------------------------------------------------------------------------------------------------
* TS_clk_fpga_1 = PERIOD TIMEGRP "clk_fpga_ | SETUP | -0.156ns
| 5.156ns | 6 | 456
1" 200 MHz HIGH 50% | HOLD
| -0.327ns | | 1274 | 256355
----------------------------------------------------------------------------------------------------------
* TS_parallella_ewrapper_link_top_io_clock_ | SETUP |
2.481ns| 1.354ns| 0| 0
gen_clkout1 = PERIOD TIMEGRP "parallella_ | HOLD |
-0.131ns| | 66| 7326
ewrapper_link_top_io_clock_gen_clkout1" T | MINPERIOD |
4.511ns| 2.155ns| 0| 0
S_clk_fpga_0 * 1.5 HIGH 50%
| | | |
|
----------------------------------------------------------------------------------------------------------
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