john-dev - Re: FPGA reprogramming on ZedBoard / Parallella board

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Message-ID: <CA+EaD-bf=Dn2msPTAbwwnHfOvw1zs=fLaMKge=A+HHBg9vcLQw@mail.gmail.com>
Date: Sat, 10 Aug 2013 11:24:07 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Cc: Sylvain Munaut <246tnt@...il.com>
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board

Hi Alexander, Sylvain,

I generated bin file from original bitstream (downloaded from parallella
ftp site). I diff it with .bin file generated from my parallella prototype
bitstream - files are identical. I used promgen to generate these files.
Than I tried with bootgen. I used zynq_fsbl_0.elf and
parallella16_prototype_uboot.elf downloaded from parallella ftp site to
generate .bin file. It's identical to files generated by promgen.

Sylvain, is there something wrong with how I generate .bin file from
bitstream?

These are commands I used to get .bin files (ISE 14.4):
bootgen -image bootimage.bif -split bin -o i BOOT.BIN
promgen -b -w -p bin -data_width 32 -u 0 parallella16_prototype.bit -o
original.bit.bin

bootimage.bif:
the_ROM_image:
{
    [bootloader]zynq_fsbl_0.elf
    top_parallella16_prototype.bit
    parallella16_prototype_uboot.elf
}

Thanks,

Katja

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