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Message-ID: <CAHL+j094=jfdEV9D1on4Cq_i-gdJyMNLk-zrDwVTtJr-3VcCGQ@mail.gmail.com>
Date: Fri, 9 Aug 2013 13:38:31 +0200
From: Sylvain Munaut <246tnt@...il.com>
To: Solar Designer <solar@...nwall.com>
Cc: john-dev@...ts.openwall.com
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board
Hi,
> Another option is to ask Sylvain Munaut (@tnt) about how he successfully
> rebuilt Parallella's bitstream.
I'm not sure of the original question, but the first rebuilt of the
bitstream I did was by following the guide published by adapteva:
http://www.adapteva.com/white-papers/parallella-platform-reference-design/
without using the ADI stuff (so no hdmi).
Then I modified some things of my own later on.
I wouldn't trust the 5%/6% ... I mean it's going to depend on the
exact ISE version, even possibly of the random seed that was used for
P&R and you're not even sure the screenshot is of exactly the code on
the github currently.
If you try to follow some Zedboard guide on the parallella, make sure
the pin assignements don't conflict with epiphany pins. You might want
to tie it's reset properly to make sure it doesn't do anything.
Cheers,
Sylvain
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