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Message-ID: <4FA05259.9080108@gmail.com>
Date: Tue, 01 May 2012 18:15:05 -0300
From: Claudio André <claudioandre.br@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: New RAR OpenCL kernel
>> Have you profiled there? To check if everything works in that machine i
>> did. Attached.
> Thanks. I wonder why there's so many NA in the output?
>
> magnum
>
I expected at least SGPRs.
Or the "driver+SDK" in bull is now "new" enough, or i misunderstood the
text below. If there are registers, i would like to see how i'm using them.
From AMD programming guide:
The instruction set for AMD Southern Islands (SI) is scalar, as are
GPRs. Also, the instruction set is no
longer clause-based. There are two types of GPRs: scalar GPRs (SGPRs) and
vector GPRs (VGPRs). Each Vector ALU has its own SGPR and VGPR pool.
There are 512 SGPRs and 256 VGPRs per Vector ALU. VGPRs handle all vector
instructions (any instruction that is handled per thread, such as
v_add_f32, a
floating point add). SGPRs are used for scalar instructions (any
instruction that
is executed once per wavefront, such as a branch, a scalar ALU
instruction, and
constant cache fetches). SGPR allocation is in increments of eight, and
VGPR
allocation is in increments of four. These increments also represent the
minimum
allocation size of these resources.
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