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Message-ID: <20110627195806.GA7892@openwall.com>
Date: Mon, 27 Jun 2011 23:58:06 +0400
From: Solar Designer <solar@...nwall.com>
To: crypt-dev@...ts.openwall.com
Subject: pcadd
Yuri, David -
I installed Xilinx ISE in an OpenVZ container with Fedora today, and I
played with it briefly. (Specifically, I installed from
Xilinx_ISE_DS_Lin_13.1_O.40d.1.1.tar.) I think this might enable us to
work on the project more closely.
I experimented with trivial code like:
module pcadd(a, b, sum);
input [7:0] a;
input [7:0] b;
output [7:0] sum;
reg [7:0] sum;
always
begin
sum = (a ^ b) + ((a & b & 8'h55) << 1);
// sum = a + b;
// sum = a ^ b;
// sum = a & b;
end
endmodule
During synthesis, I got messages like:
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
8-bit adder : 1
# Xors : 1
8-bit xor2 : 1
This is for the full/real pcadd above (the uncommented line). So it
says it sees an adder (but somehow also a xor2, even though all we are
trying to implement is just a partial adder). However, in schematic
views I don't see any attempt to use any specialized logic for the
adder. In RTL view, there are just the logic gates, which is no
surprise. In Technology view, there are just LUTs. I thought that we
had an adder with its carry chain right after LUTs in each slice, but
apparently it does not get used in my trivial example - maybe because
we'd waste those LUTs otherwise (since my module is so trivial, yet it
has many inputs/outputs)? Obviously, I am just getting into this stuff.
I noticed that there's an adder/subtracter that can be generated from
Xilinx's IP library. It offers the choice between fabric (which is what
we thought we'd be using) and DSP (probably unreasonable when we're
operating with much narrower than 48-bit data? or maybe not, because the
DSPs would otherwise be unused anyway and because they're fast?) Maybe
we have to use this in order to make use of the specialized logic?
Ditto for distributed RAM.
Alexander
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