From: Andrew Cooper Subject: x86/msr: Definitions for MSR_INTEL_CORE_THREAD_COUNT This is a model specific register which details the current configuration cores and threads in the package. Because of how Hyperthread and Core configuration works works in firmware, the MSR it is de-facto constant and will remain unchanged until the next system reset. It is a read only MSR (so unilaterally reject writes), but for now retain its leaky-on-read properties. Further CPUID/MSR work is required before we can start virtualising a consistent topology to the guest, and retaining the old behaviour is the safest course of action. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index ce22756..93cb71e 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4026,6 +4026,7 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t msr_content, wrmsrl(MSR_FLUSH_CMD, msr_content); break; + case MSR_INTEL_CORE_THREAD_COUNT: case MSR_ARCH_CAPABILITIES: /* Read-only */ case MSR_TSX_FORCE_ABORT: diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 4b257fb..2bc05f1 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2901,6 +2901,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs) wrmsrl(regs->_ecx, msr_content); break; + case MSR_INTEL_CORE_THREAD_COUNT: case MSR_INTEL_PLATFORM_INFO: case MSR_ARCH_CAPABILITIES: /* The MSR is read-only. */ diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index c2aa36e..f25f38c 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -31,6 +31,10 @@ #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSE (1<<_EFER_FFXSE) +#define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 +#define MSR_CTC_THREAD_MASK 0x0000ffff +#define MSR_CTC_CORE_MASK 0xffff0000 + /* Speculation Controls. */ #define MSR_SPEC_CTRL 0x00000048 #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)