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Date: Tue, 18 Apr 2023 09:28:49 +0800
From: 王洪亮 <wanghongliang@...ngson.cn>
To: musl@...ts.openwall.com
Subject: add loongarch64 port v7.
Hi,
I published 0001-add-loongarch64-port-v7.patch,as shown in the
attachment.
Fixed 3 issues:
1.Glibc has finally decided not to break their api to make it
consistent with linux uapi.so I modify the mcontext member to
match current glibc,and sigcontext to match kernel.
I reuse __attribute__((__aligned__(16))) to describe extcontext[]
instead of use the __uc_pad in ucontext_t.I think __uc_pad can
only ensure the ucontext_t.uc_mcontext is 16 alignment and
uc_mcontext.__extcontext[] is 16 alignment,But it cannot ensure
the sigcontext.sc_extcontext[] and mcontext.__extcontext[]
(only mcontext,not ucontext_t.uc_mcontext) is 16 alignment.this
is inconsistent with kernel and against the design intention
(extcontext[] used for 128bit vector register,need 16 alignment).
---
arch/loongarch64/bits/signal.h | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/arch/loongarch64/bits/signal.h b/arch/loongarch64/bits/signal.h
index 83d40b1f..c56fe243 100644
--- a/arch/loongarch64/bits/signal.h
+++ b/arch/loongarch64/bits/signal.h
@@ -6,14 +6,27 @@
#define SIGSTKSZ 16384
#endif
+#if defined(_GNU_SOURCE) || defined(_BSD_SOURCE)
typedef unsigned long greg_t, gregset_t[32];
-typedef struct sigcontext {
+struct sigcontext {
unsigned long sc_pc;
- gregset_t sc_regs;
- unsigned int sc_flags;
- unsigned long sc_extcontext[];
+ unsigned long sc_regs[32];
+ unsigned int sc_flags;
+ unsigned long sc_extcontext[] __attribute__((__aligned__(16)));
+};
+
+typedef struct {
+ unsigned long __pc;
+ unsigned long __gregs[32];
+ unsigned int __flags;
+ unsigned long __extcontext[] __attribute__((__aligned__(16)));
} mcontext_t;
+#else
+typedef struct {
+ unsigned long __space[34];
+} mcontext_t;
+#endif
struct sigaltstack {
void *ss_sp;
@@ -23,11 +36,10 @@ struct sigaltstack {
typedef struct __ucontext
{
- unsigned long uc_flags;
+ unsigned long __uc_flags;
struct __ucontext *uc_link;
stack_t uc_stack;
sigset_t uc_sigmask;
- long __uc_pad;
mcontext_t uc_mcontext;
} ucontext_t;
--
2.31.1
---
arch/loongarch64/pthread_arch.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/loongarch64/pthread_arch.h
b/arch/loongarch64/pthread_arch.h
index 3224c14f..28fbfcd1 100644
--- a/arch/loongarch64/pthread_arch.h
+++ b/arch/loongarch64/pthread_arch.h
@@ -8,4 +8,4 @@ static inline uintptr_t __get_tp()
#define TLS_ABOVE_TP
#define GAP_ABOVE_TP 0
#define DTP_OFFSET 0
-#define MC_PC sc_pc
+#define MC_PC __pc
--
2.31.1
2.Fixed compile error when use clang.
The compile error such as:
../src/feny/loongarch64/fenv.S:10:13:error: invalid operand
for instruction
movgr2fcsr $r0，$t1;
^
---
src/fenv/loongarch64/fenv.S | 27 +++++++++++++++++----------
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/src/fenv/loongarch64/fenv.S b/src/fenv/loongarch64/fenv.S
index 175eb8b7..47ff4046 100644
--- a/src/fenv/loongarch64/fenv.S
+++ b/src/fenv/loongarch64/fenv.S
@@ -1,13 +1,20 @@
#ifndef __loongarch_soft_float
+#ifdef __clang__
+#define FCSR $fcsr0
+#else
+#define FCSR $r0
+#endif
+
+
.global feclearexcept
.type feclearexcept,@function
feclearexcept:
li.w $t0, 0x1f0000
and $a0, $a0, $t0
- movfcsr2gr $t1, $r0
+ movfcsr2gr $t1, FCSR
andn $t1, $t1, $a0
- movgr2fcsr $r0, $t1
+ movgr2fcsr FCSR, $t1
li.w $a0, 0
jr $ra
@@ -16,9 +23,9 @@ feclearexcept:
feraiseexcept:
li.w $t0, 0x1f0000
and $a0, $a0, $t0
- movfcsr2gr $t1, $r0
+ movfcsr2gr $t1, FCSR
or $t1, $t1, $a0
- movgr2fcsr $r0, $t1
+ movgr2fcsr FCSR, $t1
li.w $a0, 0
jr $ra
@@ -27,14 +34,14 @@ feraiseexcept:
fetestexcept:
li.w $t0, 0x1f0000
and $a0, $a0, $t0
- movfcsr2gr $t1, $r0
+ movfcsr2gr $t1, FCSR
and $a0, $t1, $a0
jr $ra
.global fegetround
.type fegetround,@function
fegetround:
- movfcsr2gr $t0, $r0
+ movfcsr2gr $t0, FCSR
andi $a0, $t0, 0x300
jr $ra
@@ -44,17 +51,17 @@ fegetround:
__fesetround:
li.w $t0, 0x300
and $a0, $a0, $t0
- movfcsr2gr $t1, $r0
+ movfcsr2gr $t1, FCSR
andn $t1, $t1, $t0
or $t1, $t1, $a0
- movgr2fcsr $r0, $t1
+ movgr2fcsr FCSR, $t1
li.w $a0, 0
jr $ra
.global fegetenv
.type fegetenv,@function
fegetenv:
- movfcsr2gr $t0, $r0
+ movfcsr2gr $t0, FCSR
st.w $t0, $a0, 0
li.w $a0, 0
jr $ra
@@ -65,7 +72,7 @@ fesetenv:
addi.d $t0, $a0, 1
beq $t0, $r0, 1f
ld.w $t0, $a0, 0
-1: movgr2fcsr $r0, $t0
+1: movgr2fcsr FCSR, $t0
li.w $a0, 0
jr $ra
--
2.31.1
3.Modify the __pad of stat to __pad1 to make it consistent with
current glibc.
---
arch/loongarch64/bits/stat.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/loongarch64/bits/stat.h b/arch/loongarch64/bits/stat.h
index b7f4221b..b604fb8f 100644
--- a/arch/loongarch64/bits/stat.h
+++ b/arch/loongarch64/bits/stat.h
@@ -6,7 +6,7 @@ struct stat {
uid_t st_uid;
gid_t st_gid;
dev_t st_rdev;
- unsigned long __pad;
+ unsigned long __pad1;
off_t st_size;
blksize_t st_blksize;
int __pad2;
--
2.37.1
View attachment "0001-add-loongarch64-port-v7.patch" of type "text/x-patch" (44543 bytes)
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