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Message-ID: <51118a06-8aa0-5da8-e04f-e94c83fc7de0@codeaurora.org>
Date: Tue, 14 Jun 2016 09:35:05 -0700
From: "Zhao, Weiming" <weimingz@...eaurora.org>
To: musl@...ts.openwall.com
Subject: Re: build musl for armv7m
I'll fix the indention.
Why do we use .word encoded instruction? Clang's integrated-as can
encode the instruction correctly. Is that some workaround with some
compiler?
Regarding " The second one(teqeq) is using the result of the strexeq,
not the result of thesubs.":
strexeq won't change flag register:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABFFBJB.html
If it would, the execution of teqeq will depend on the conditionally
executed "strexeq", is that expected?
Thanks,
Weiming
On 6/14/2016 7:38 AM, Rich Felker wrote:
> On Tue, Jun 14, 2016 at 01:49:40AM -0700, weimingz@...eaurora.org wrote:
>> diff --git a/src/setjmp/arm/longjmp.s b/src/setjmp/arm/longjmp.s
>> index e28d8f3..5c85cba 100644
>> --- a/src/setjmp/arm/longjmp.s
>> +++ b/src/setjmp/arm/longjmp.s
>> @@ -7,8 +7,11 @@ _longjmp:
>> longjmp:
>> mov ip,r0
>> movs r0,r1
>> + it eq
>> moveq r0,#1
>> - ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp,sp,lr}
>> + ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp}
>> + ldr sp, [ip]!
>> + ldr lr, [ip]!
> Small note: your indention is inconsistent -- using a single space
> instead of a tab.
>
> In my earlier work trying to get an all-thumb build working, I had
> tried doing this as:
>
> + ldmia ip!, {r2,v1,v2,v3,v4,v5,v6,sl,fp,lr}
> + mov sp,r2
>
> which might be marginally faster but of course it reorders the fields
> in the jmp_buf. Nothing should be depending on them anyway but I like
> your version better I think. Likewise for setjmp.
>
>> diff --git a/src/thread/arm/atomics.s b/src/thread/arm/atomics.s
>> index 673fc03..05fd9b9 100644
>> --- a/src/thread/arm/atomics.s
>> +++ b/src/thread/arm/atomics.s
>> @@ -49,6 +49,7 @@ __a_cas_dummy:
>> mov r3,r0
>> ldr r0,[r2]
>> subs r0,r3,r0
>> + it eq
>> streq r1,[r2]
>> bx lr
>> .global __a_cas_v6
>> @@ -58,6 +59,7 @@ __a_cas_v6:
>> mcr p15,0,r0,c7,c10,5
>> 1: .word 0xe1920f9f /* ldrex r0,[r2] */
>> subs r0,r3,r0
>> + itt eq
>> .word 0x01820f91 /* strexeq r0,r1,[r2] */
>> teqeq r0,#1
>> beq 1b
> You're ignoring that the .word-encoded instruction is not valid thumb,
> and that the two 'eq' conditions are independent. The second one
> (teqeq) is using the result of the strexeq, not the result of the
> subs. But there are much deeper reasons this file cannot work as thumb
> without significant changes: the arithmetic on pc is not
> thumb-compatible.
>
>> @@ -70,6 +72,7 @@ __a_cas_v7:
>> .word 0xf57ff05b /* dmb ish */
>> 1: .word 0xe1920f9f /* ldrex r0,[r2] */
>> subs r0,r3,r0
>> + itt eq
>> .word 0x01820f91 /* strexeq r0,r1,[r2] */
>> teqeq r0,#1
>> beq 1b
> Same here.
>
> There's also the matter of the code to read the thread pointer, which
> requires a special CP15 register that cortex-m's lack, I think. I
> don't see any alternate way to do this functionality (and it would be
> ABI-incompatible anyway) so I think the kernel (or bare-metal
> undefined instruction exception trap) needs to just trap and emulate
> it.
>
> Rich
--
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